ongelma-koodi tuottavan toivottuja lukot

[indomitable12345]

Katso attatched verilog source.when yritän koota tämän moduulin kanssa qu (at) rtus, ei-toivotun lukot ovat johtaneet kaikki tuotoksen verkkojen .. se on lausahtaen että verkot add1_temp, add2_temp, go_temp jne. säilyttää aikaisemman arvoon yhden tai useamman polkuja aina rakentaa ... kukaan voi auttaa minua tämän ongelman ratkaisemiseksi?

 

[news]

Zarówno internet, jak i obecne w nim zagrożenia, podlegają ciągłym zmianom. Właśnie dlatego, bezpieczeństwo w sieci wymaga stworzenia w miejsce prostych "do's and don'ts", odpowiedniego zbioru zachowań. Sophos prezentuje trzy pytania, które powinniśmy sobie zadać poruszając się w internecie - niezależnie od tego, czy przeglądamy strony, wyrażamy zgodę na warunki użytkowania, zamieszczamy zdjęcia czy po prostu sprawdzamy skrzynkę mailową.

Read more...

 

[nand_gates]

Tässä olen lähettämistä koodia.Please post ur koodeja näin.sijaan luoda
Word-ja sitten lataamalla.Koodi on sisennetty porperly.Tein sen tällä kertaa.

Täällä ur koodi jos ilmoitus olet sekoittaminen sekä seqential sekä
kombinatorisista tehtäviä.Tämä on erittäin hyvä esimerkki erittäin huono verilog koodaus
synteesiin.Olen pahoillani, että.Ensin miettiä logiikka haluat
ja käyttää HDL (verilog) vain kuvata sitä.

Koodi:

"ajassa 1 ns / 1 ps

moduuli control_unit_statemac (add1_temp,

add2_temp,

op_code_temp,

sel_temp,

d_bus,

push_temp,

pop_temp,

go_temp,

clkin_temp,

pclk, rs,

CLK,

RST,

int0,

int1,

ir,

dz,

z

cy);output [13:0] add1_temp, add2_temp;

output [2:0] op_code_temp;

output [3:0] sel_temp;

InOut [15:0] d_bus;

output pclk, go_temp, push_temp, pop_temp, clkin_temp, RS;

input CLK, RST, int0, int1, dz, z, CY;

input [21:0] ir;reg [13:0] add1_temp, add2_temp;

reg [2:0] op_code_temp;

reg [3:0] sel_temp;

reg [15:0] d_out, d_bus_temp;

reg pclk, push_temp, pop_temp, go_temp, clkin_temp, RS;parametri reset = 18'd0,

= 18'd1,

viitearvo b = 18'd2,

C = 18'd4,

d = 18'd8,

e = 18'd16,

, f = 18'd32,

g = 18'd64,

h = 18'd128,

i = 18'd256,

j = 18'd512,

K = 18'd1024,

L = 18'd2048,

M = 18'd4096,

n = 18'd8192,

O = 16384,

p = 18'd32768,

q = 18'd65536,

R = 18'd131072;parametri a_add = 7'b0110010,

b_add = 7'b0110011,

c_add = 7'b0110100,

pc_add = 7'b0010000,

stack_add = 7'b0101111;reg [17:0] p_state, n_state;aina @ (posedge CLK) alkaa

jos (RST)

p_state <= reset;

muuten

p_state <= n_state;

loppuaina @ * alkaa / / (p_state)

tapauksessa (p_state)

Reset: alkaa

n_state <=;

op_code_temp <= 3'bzzz;

add1_temp [13:0] <= 14'hzzzz;

add2_temp [13:0] <= 14'hzzzz;

go_temp <= 1'b0;

pclk <= 1'b0;

push_temp <= 1'b0;

pop_temp <= 1'b0;

clkin_temp <= 1'b0;

rs <= 1'b1;

loppu: alkaa

casex (IR)

22'b000001xxxxxxxxxxxxxxxx: alkaa

n_state <= L;

@ (posedge CLK) alkaa

add1_temp [6:0] <= ir [14:8];

add1_temp [13:7] <= stack_add;

sel_temp [3:0] <= 4'b0011;

push_temp <= 1'b1;

/ / add2_temp [13:0] <= 14'bzzzzzzzzzzzzzz;

/ / d_out [15:0] <= 16'hzzzz;

/ / op_code_temp [2:0] <= 3'bzzz;

/ * pop_temp <= 1'b0;

go_temp <= 1'b0;

clkin_temp <= 1'b0 * / lopussa

pclk <= 1'b0;

rs <= 1'b0;

loppu22'b000010xxxxxxxxxxxxxxxx: alkaa

n_state <= m;

@ (posedge CLK) alkaa

add1_temp [6:0] <= stack_add;

add1_temp [13:7] <= ir [14:8];

pop_temp <= 1'b1;

sel_temp [3:0] <= 4'b0011;

/ * add2_temp [13:0] <= 14'bzzzzzzzzzzzzzz;

push_temp <= 1'b0;

op_code_temp [2:0] <= 3'bzzz;

go_temp <= 1'b0;

d_out [15:0] <= 16'hzzzz;

clkin_temp <= 1'b0 * /

loppu

pclk <= 1'b0;

rs <= 1'b0;

loppu22'b001xxxxxxxxxxxxxxxxxxx: alkaa

n_state <= b;

@ (posedge CLK) alkaa

add1_temp [13:7] <= a_add;

add1_temp [6:0] <= ir [6:0];

add2_temp [13:7] <= b_add;

add2_temp [6:0] <= ir [14:8];

sel_temp [3:0] <= 4'b1111;

/ * d_out [15:0] <= 16'hzzzz;

op_code_temp [2:0] <= 3'bzzz;

go_temp <= 1'b0;

push_temp <= 1'b0;

pop_temp <= 1'b0;

clkin_temp <= 1'b0 * /

loppu

pclk <= 1'b0;

rs <= 1'b0;

loppu22'b010xxxxxxxxxxxxxxxxxxx: alkaa

n_state <= d;

@ (posedge CLK) alkaa

d_out [7:0] <= ir [7:0];

add1_temp [13:7] <= a_add;

/ / add1_temp [6:0] <= 7'bzzzzzzz;

add2_temp [13:7] <= b_add;

add2_temp [6:0] <= ir [14:8];

sel_temp [3:0] <= 4'b1110;

/ * d_out [15:8] <= 8'hzz;

op_code_temp [2:0] <= 3'bzzz;

go_temp <= 1'b0;

push_temp <= 1'b0;

pop_temp <= 1'b0;

clkin_temp <= 1'b0 * /

loppu

pclk <= 1'b0;

rs <= 1'b0;

loppu22'b011xxxxxxxxxxxxxxxxxxx: alkaa

n_state <= e;

@ (posedge CLK) alkaa

add1_temp [13:7] <= ir [14:8];

add1_temp [6:0] <= ir [6:0];

sel_temp [3:0] <= 4'b0011;

/ * add2_temp [13:0] <= 14'bzzzzzzzzzzzzzz;

d_out [15:0] <= 16'hzzzz;

op_code_temp <= 3'bzzz;

go_temp <= 1'b0;

pclk <= 1'b0;

push_temp <= 1'b0;

pop_temp <= 1'b0;

clkin_temp <= 1'b0 * /

loppu

pclk <= 1'b0;

rs <= 1'b0;

loppu22'b100xxxxxxxxxxxxxxxxxxx: alkaa

n_state <= g;

@ (posedge CLK) alkaa

d_out [7:0] <= ir [7:0];

add1_temp [13:7] <= ir [14:8];

sel_temp [3:0] <= 4'b0010;

/ * add1_temp [6:0] <= 7'bzzzzzzz;

add2_temp [13:0] <= 14'bzzzzzzzzzzzzzz;

op_code_temp [2:0] <= 3'bzzz;

d_out [15:8] <= 8'hzz;

go_temp <= 1'b0;

push_temp <= 1'b0;

pop_temp <= 1'b0;

clkin_temp <= 1'b0 * / lopussa

pclk <= 1'b0;

rs <= 1'b0;

loppu22'b101001xxxxxxxxxxxxxxxx: alkaa

n_state <= h;

@ (posedge CLK) alkaa

add1_temp [13:7] <= stack_add;

add1_temp [6:0] <= pc_add;

sel_temp [3:0] <= 4'b0011;

/ * add2_temp [13:0] <= 14'bzzzzzzzzzzzzzz;

op_code_temp [2:0] <= 3'bzzz;

d_out [15:0] <= 16'hzzzz;

go_temp <= 1'b0;

push_temp <= 1'b0;

pop_temp <= 1'b0;

clkin_temp <= 1'b0 * / lopussa

pclk <= 1'b0;

rs <= 1'b0;

loppu22'b101010xxxxxxxxxxxxxxxx: alkaa

n_state <= j;

@ (posedge CLK) alkaa

add1_temp [13:7] <= pc_add;

add1_temp [6:0] <= stack_add;

pop_temp <= 1'b1;

sel_temp [3:0] <= 4'b0011;

/ * add2_temp [13:0] <= 14'bzzzzzzzzzzzzzz;

d_out [15:0] <= 16'hzzzz;

op_code_temp [2:0] <= 3'bzzz;

go_temp <= 1'b0;

push_temp <= 1'b0;

clkin_temp <= 1'b0 * / lopussa

pclk <= 1'b0;

rs <= 1'b0;

loppu22'b110xxxxxxxxxxxxxxxxxxx: alkaa

n_state <= n;

@ (posedge CLK) alkaa

add1_temp [13:7] <= pc_add;

d_out [7:0] <= ir [15:8];

sel_temp [3:0] <= 4'b0010;

/ * add1_temp [6:0] <= 7'bzzzzzzz;

add2_temp [13:0] <= 14'bzzzzzzzzzzzzzz;

op_code_temp [2:0] <= 3'bzzz;

d_out [15:8] <= 8'hzz;

go_temp <= 1'b0;

push_temp <= 1'b0;

pop_temp <= 1'b0;

clkin_temp <= 1'b0 * /

loppu

pclk <= 1'b0;

rs <= 1'b0;

loppu22'b111001xxxxxxxxxxxxxxxx: alkaa

pclk <= 1'b0;

rs <= 1'b0;

jos (dz == 0) alkaa

n_state <= O; clkin_temp <= 1'b1;

loppu

muuten

n_state <= q;

loppu22'b111010xxxxxxxxxxxxxxxx: alkaa

pclk <= 1'b0;

rs <= 1'b0;

if (z! = 0)

n_state <= O;

muuten

n_state <= q;

loppu22'b111011xxxxxxxxxxxxxxxx: alkaa

if (z == 0) n_state <= O;

else n_state <= q;

pclk <= 1'b0;

rs <= 1'b0;

loppu22'b111100xxxxxxxxxxxxxxxx: alkaa

pclk <= 1'b0;

rs <= 1'b0;

if (cy == 0)

n_state <= O;

muuten

n_state <= q;

loppu22'b111101xxxxxxxxxxxxxxxx: alkaa

pclk <= 1'b0;

rs <= 1'b0;

if (cy! = 0)

n_state <= O;

muuten

n_state <= q;

loppudefault: n_state <= reset;endcaseloppub: alkaa

n_state <= c;

@ (posedge CLK) alkaa

/ / add2_temp [13:0] <= 14'bzzzzzzzzzzzzzz;

/ / add1_temp [13:0] <= 14'bzzzzzzzzzzzzzz;

sel_temp [3:0] <= 4'b0000;

op_code_temp <= ir [18:16]

go_temp <= 1'b1;

loppu

loppuC: alkaa

n_state <=;

@ (posedge CLK) alkaa

add1_temp [13:7] <= ir [14:8];

add1_temp [6:0] <= c_add;

sel_temp [3:0] <= 4'b0011;

op_code_temp <= 3'bzzz;

go_temp <= 1'b0;

loppu

pclk <= 1'b1;

loppud: alkaa

n_state <= c;

@ (posedge CLK) alkaa

/ / add2_temp [13:0] <= 14'bzzzzzzzzzzzzzz;

/ / add1_temp [13:7] <= 7'bzzzzzzz;

sel_temp [3:0] <= 4'b0000;

op_code_temp <= ir [18:16]

go_temp <= 1'b1;

loppu

loppue: alkaa

n_state <= f;

@ (posedge CLK)

sel_temp [3:0] <= 4'b0000;

/ / add1_temp [13:0] <= 14'bzzzzzzzzzzzzzz;

loppuf: alkaa

n_state <=;

pclk <= 1'b1;

loppug: alkaa

n_state <= f;

@ (posedge CLK) alkaa

d_out [7:0] <= 8'hzz;

sel_temp [3:0] <= 4'b0000;

/ / add1_temp [13:7] <= 7'bzzzzzzz;

loppu

loppuh: alkaa

n_state <= i;

@ (posedge CLK)

push_temp <= 1'b1;

loppui: alkaan_state <=;

@ (posedge CLK) alkaa

add1_temp [13:7] <= pc_add;

d_out [7:0] <= ir [15:8];

sel_temp [3:0] <= 4'b0010;

/ / add1_temp [6:0] <= 7'bzzzzzzz;

loppu

loppuj: alkaan_state <= k;

@ (posedge CLK) alkaa

pop_temp <= 1'b0;

sel_temp [3:0] <= 4'b0000;

loppu

loppuK: alkaa

n_state <=;

loppuL: alkaa

n_state <= f;

@ (posedge CLK) alkaa

push_temp <= 1'b0;

sel_temp [3:0] <= 4'b0000;

loppu

loppuM: alkaa

n_state <= f;

@ (posedge CLK) alkaa

pop_temp <= 1'b0;

sel_temp [3:0] <= 4'b0000;

loppu

loppuN: alkaa

n_state <= k;

@ (posedge CLK) alkaa

sel_temp [3:0] <= 4'b0000;

/ / add1_temp [13:7] <= 7'bzzzzzzz;

d_out [7:0] <= 8'hzz;

loppu

loppuO: alkaa

n_state <= p;

@ (posedge CLK) alkaa

sel_temp [3:0] <= 4'b0010;

add1_temp [13:7] <= pc_add;

d_out [7:0] <= ir [15:8];

loppu

loppuP: alkaa

n_state <=;

@ (posedge CLK) alkaa

sel_temp [3:0] <= 4'b0000;

/ / add1_temp [13:7] <= 7'bzzzzzzz;

d_out [7:0] <= 8'hzz;

loppu

loppuQ: alkaa

n_state <= r;

/ * @ (posedge CLK) alkaa

add1_temp [13:0] <= 14'bzzzzzzzzzzzzzz;

add2_temp [13:0] <= 14'bzzzzzzzzzzzzzz;

d_out [15:0] <= 16'hzz;

push_temp <= 1'b0;

pop_temp <= 1'b0;

go_temp <= 1'b0;

clkin_temp <= 1'b0;

op_code_temp [2:0] <= 3'bzzz; loppuun * /

loppuR: alkaa

n_state <=;

/ * @ (posedge CLK) alkaa

add1_temp [13:0] <= 14'bzzzzzzzzzzzzzz;

add2_temp [13:0] <= 14'bzzzzzzzzzzzzzz;

d_out [15:0] <= 16'hzz;

push_temp <= 1'b0;

pop_temp <= 1'b0;

go_temp <= 1'b0;

clkin_temp <= 1'b0;

op_code_temp [2:0] <= 3'bzzz; loppuun * /

pclk <= 1'b1;

loppudefault: n_state <= reset;

endcase/ * @ (posedge CLK)

aloittaa

ADD1 [13:0] <= add1_temp [13:0];

ADD2 [13:0] <= add2_temp [13:0];

/ / data [15:0] <= d_bus_temp [15:0];

op_code [2:0] <= op_code_temp [2:0];

Push <= push_temp;

Pop <= pop_temp;

clkin <= clkin_temp;

go <= go_temp;

d_bus_temp <= d_out [15:0];

loppu

* /

varten / / aina @ *aina @ (posedge CLK)

d_bus_temp [15:0] <= d_out [15:0];

määrittää d_bus [15:0] = d_bus_temp [15:0];

endmodule